1. Twin DSP16000 dual-MAC (multiply and accumulate) cores for high throughput: * 1140 MMACs (million multiply and accumulates) per second at 285 MHz * Dual 16-bit by 16-bit MACs per cycle per core 322K x 16 total on-chip RAM2. Centralized direct memory access unit (DMAU): * Transparent peripheral-to- memory and memory-to-memory transfers * Optimized utilization of DSP MIPS— Simplifies management of system data flow3. 32-bit system and external memory interface (SEMI) supports 16-bit or 32-bit synchronous or asynchronous memories4.16-bit parallel interface unit (PIU) with direct memory access (DMA) provides host access to all DSP memory5. Two enhanced serial I/O units (SIU0 and SIU1) with DMA: * Compatible with TDM highways such as E1/T1and ST-bus * Hardware support for μ-law and A-law companding6. Core messaging units (MGU0 and MGU1) for interprocessor communication 7. On-chip, programmable, PLL clock synthesizer eliminates need for high-speed clock input8. Two 7-bit control I/O interfaces (BIOs) for increased flexibility and lower system costs9. Two IEEE 1149.1 test ports (JTAG boundary scan)10. Full-speed, in-circuit, emulation hardware on-chip for efficient application development11. Supported by DSP164XX software and hardware development tools12. Low power: * 1.2 V internal supply for power efficiency * 3.3 V I/O pin supply for compatibility13. Small-footprint, 208-ball PBGA package (17 mm x 17 mm, 1.0 mm ball pitch)14. Code compatible with the DSP16210 and DSP16410 devices
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